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ez-usb at2lp? usb 2.0 to ata/atapi bridge CY7C68300B/cy7c68301b cy7c68320/cy7c68321 cypress semiconductor corporation 3901 north first street san jose , ca 95134 408-943-2600 document 38-08033 rev. *c revised february 14, 2005 1.0 features (CY7C68300B/cy7c68301b and cy7c68320/cy7c68321) fixed-function mass storage device?requires no firmware code two power modes: self-powered and usb bus-powered to enable bus powered cf readers and truly portable usb hard drives certified compliant for usb 2.0 (tid# 40460273), the usb mass storage class, and the usb mass storage class bulk-only transport (bot) specification operates at high (480-mbps) or full (12-mbps) speed usb complies with ata/atapi-6 specification supports 48-bit addressing for large hard drives supports ata security features supports all ata commands via atacb function supports mode page 5 for bios boot support supports atapi serial number vpd page retrieval for digital rights management (drm) compatibility supports pio modes 0, 3, 4, multiword dma mode 2, and udma modes 2, 3, 4 uses one external serial eeprom for storage of usb descriptors and device configuration data ata interface irq signal support support for one or two ata/atapi devices support for compactflash and one ata/atapi device can place the ata interface in high-impedance (hi-z) to allow sharing of the ata bus with another controller (e.g., an ieee-1394 to ata bridge chip or mp3 decoder) support for board-level manufacturing test via usb interface low-power 3.3v operation fully compatible with native usb mass storage class drivers cypress mass storage class drivers available for windows (98se, me, 2000, xp) and mac os x 1.1 features (cy7c68320/cy7c68321 only) supports hid interface or custom gpios to enable features such as single button backup, power-off, led-based notifi- cation, etc. lead-free 56-pin qfn and 100-pin tqfp packages cy7c68321 is ideal for battery-powered designs cy7c68320 is ideal for self- and bus-powered designs 1.2 features (CY7C68300B/cy7c68301b only) pin-compatible with cy7c68300a (using backward compatibility mode) lead-free 56-pin ssop and 56-pin qfn packages cy7c68301b is ideal for battery-powered designs CY7C68300B is ideal for self- and bus-powered designs 2.0 block diagram usb 2.0 xcvr cy smar t us b fs/hs engine 4 kby te fifo pl l i2 c b us co nt r ol le r ata in te r f ac e logic dat a co nt r ol 24 mhz xtal 16 bit ata data a t a _ e n ( a t a i n t e r f a c e 3 - s t a t e ) vbus d+ d- internal control logic reset scl sda ata interface control signals misc control signals figure 2-1. block diagram
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 2 of 36 3.0 applications the CY7C68300B/301b and cy7c68320/321 implement a usb 2.0 bridge for all ata/atapi-6 compliant mass storage devices, such as the following. hard drives cd-rom, cd-r/w dvd-rom, dvd-ram, dvd+/?r/w mp3 players personal media players compactflash microdrives tape drives personal video recorders the CY7C68300B/301b and cy7c68320/321 support one or two devices in the following configurations. ata/atapi master only ata/atapi slave only ata/atapi master and slave compactflash only ata/atapi slave and compactflash or other removable ide master 3.1 additional resources cy4615b ez-usb at2lp reference design kit usb specification version 2.0 ata specification t13/1410d rev 3b usb mass storage class bulk only transport specification , www.usb.org 4.0 introduction the ez-usb at2lp ? (CY7C68300B/cy7c68301b and cy7c68320/cy7c68321) implements a fixed function bridge between one usb port and one or two ata- or atapi-based mass storage device ports. this bridge adheres to the mass storage class bulk-only transport specification and is intended for bus- and self-powered devices. the at2lp is the latest addition to the cypress usb mass storage portfolio, and is an ideal cost- and power-reduction path for designs that previously used the isd-300a1, isd- 300lp, or ez-usb at2. specifically, the CY7C68300B/cy7c68301b includes a mode that makes it pin-for-pin compatible with the ez- usb at2 (cy7c68300a) . the usb port of the CY7C68300B/301b and cy7c68320/321 (at2lp) are connected to a host computer directly or via the downstream port of a usb hub. host software issues commands and data to the at2lp and receives status and data from the at2lp using standard usb protocol. the ata/atapi port of the at2lp is connected to one or two mass storage devices. a 4-kbyte buffer maximizes ata/atapi data transfer rates by minimizing losses due to device seek times. the ata interface supports ata pio modes 0, 3, and 4, multiword dma mode 2 and ultra dma modes 2, 3, and 4. the device initialization process is configurable, enabling the at2lp to initialize ata/atapi devices without software inter- vention. 5.0 68300a compatibility the CY7C68300B/301b and cy7c68320/321 are available in three package types that are pictured in the following sections. as mentioned above, the CY7C68300B/301b contains a backward compatibility mode that allows the CY7C68300B/301b to be used in existing ez-usb at2 (cy7c68300a) designs. please refer to the logic flow below for more information on the pinout selection process. read eeprom eeprom signature 0x4d4d? yes set ez-usb at2 (cy7c68300a) pinout set ez-usb at2lp (CY7C68300B) pinout no normal operation figure 5-1. simplified startup flowchart (68300b only)
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 3 of 36 5.1 pin diagrams 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 56 55 54 53 atapuen ( gnd ) vcc gnd iordy dma rq avcc xtalout xtalin agnd vcc dplus dminus gnd vcc gnd pwr500# ( pu 10k ) gnd ( reserved ) scl sda vcc dd0 dd1 dd2 dd3 dd13 dd14 dd15 gnd ez-usb at2lp CY7C68300B cy7c68301b 56-pin ssop dd8 ( ata_en ) v bus_a ta _ena ble vcc reset# gnd a reset# ( vbus_pw r_valid ) da2 cs1# cs0# ( da2 ) drvpwrvld da 1 da 0 intrq vcc dma ck# dior# diow# gnd vcc gnd dd7 dd6 dd5 dd4 dd12 dd11 dd10 dd9 figure 5-2. 56-pin ssop pinout (CY7C68300B/cy7c68301b only) note: labels in italics denote pin functionality during cy7c68300a compatibility mode.
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 4 of 36 reset# gnd areset# da2 ( vbus_pwr_valid ) cs1# cs0# drvpwrvld ( da2 ) da1 da0 intrq vcc dmack# dior# diow# iordy dmarq avcc xtal ou t xta l i n agnd vcc dplus dminus gnd vcc gnd (pu 10k) pwr500# gnd 15 16 17 18 19 20 21 22 23 24 25 26 27 28 scl sda vcc dd0 dd1 dd2 dd3 dd4 dd5 dd6 dd7 gnd vcc gnd 42 41 40 39 38 37 36 35 34 33 32 31 30 29 56 55 54 53 52 51 50 49 48 47 46 45 44 43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 gnd vcc atapuen ( nc ) gnd dd15 dd14 dd13 dd12 dd11 dd10 dd9 dd8 vbus_ata_enable ( ata_en ) vcc ez-usb at2lp CY7C68300B cy7c68301b 56-pin qfn note: italic labels denote pin functionality during cy7c68300a compatibility mode. figure 5-3. 56-pin qfn pinout (CY7C68300B/cy7c68301b)
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 5 of 36 gnd vcc gpio2 gnd dd15 dd14 dd13 dd12 dd11 dd10 dd9 dd8 vbus_ata_enable vcc reset# gnd areset# da2 cs1# cs0# gpio0 da1 da0 intrq vcc dmack# dior# diow# iordy dmarq avcc xtal ou t xta l i n agnd vcc dplus dminus gnd vcc gnd gpio1 gnd scl sda vcc dd0 dd1 dd2 dd3 dd4 dd5 dd6 dd7 gnd vcc gnd 15 16 17 18 19 20 21 22 23 24 25 26 27 28 42 41 40 39 38 37 36 35 34 33 32 31 30 29 56 55 54 53 52 51 50 49 48 47 46 45 44 43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ez-usb at2lp cy7c68320 cy7c68321 56-pin qfn figure 5-4. 56-pin qfn pinout (cy7c68320/cy7c68321)
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 6 of 36 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 dd8 vbus_ata_enable vcc reset# nc gnd areset# da 2 cs1# cs0# drv pwrv ld da 1 da 0 intrq vcc gnd nc nc v buspwrd nc nc nc lowpwr# nc dma ck# dior# diow# vcc nc nc vcc gnd iordy dma rq gnd gnd gnd gnd avcc xtalout xtalin agnd nc nc nc vcc dplus dminus gnd vcc gnd sysirq gnd gnd gnd pwr50 0# gnd nc scl sda 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ez-usb at2lp cy7c68320b cy7c68321b 100-pin tqfp nc nc vcc dd0 dd1 dd2 dd3 vcc gnd nc gnd nc gnd dd4 dd5 dd6 dd7 gnd vcc gnd atapuen gnd dd15 dd14 dd13 dd12 gnd gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 nc nc vcc gnd dd11 dd10 dd9 figure 5-5. 100-pin tqfp pinout (cy7c68320/cy7c68321 only)
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 7 of 36 5.2 pin descriptions the following table lists the pinouts for the 56-pin ssop, 56- pin qfn and 100-pin tqfp package options for the at2lp. please refer to the pin diagrams in section for differences between the 68300b/01b and 68320/321 pinouts for the 56- pin packages. for information on the cy7c68300a pinout, please refer to the cy7c68300a data sheet that is found in the ?ez-usb at2? folder of the cy4615b reference design kit cd. table 5-1. at2lp pin descriptions note: (italics pin names denote pin functionality during cy7c68300a-compatibility mode) 56 ssop 56 qfn 100 tqfp pin name pin type default state at start-up pin description 1 50 96 dd13 i/o [1] hi-z ata data bit 13 . 2 51 97 dd14 i/o [1] hi-z ata data bit 14 . 3 52 98 dd15 i/o [1] hi-z ata data bit 15 . 4 53 99 gnd gnd ground . 5 54 [3] 100 [3] atapuen ( nc ) i/o ata pull-up voltage source for bus-powered applica- tions (see section 5.3.10). alternate function : input when the eeprom config- uration byte 8 has bit 7 set to one. the input value is reported through ep1in (byte 0, bit 2). 6 55 1 v cc pwr v cc . connect to 3.3v power source. 7 56 2 gnd gnd ground . 8 1 3 iordy i [1] input ata control . 9 2 4 dmarq i [1] input ata control . n/a n/a 5 6 7 8 gnd ground . 10 3 9 av cc pwr analog v cc . connect to v cc through the shortest path possible. 11 4 10 xtalout xtal xtal 24-mhz crystal output (see section ). 12 5 11 xtalin xtal xtal 24-mhz crystal input (see section ). 13 6 12 agnd gnd analog ground . connect to ground with as short a path as possible. n/a n/a 13 14 15 nc no connect . 14 7 16 v cc pwr v cc . connect to 3.3v power source. 15 8 17 dplus i/o hi-z usb d+ signal (see section 5.3.1). 16 9 18 dminus i/o hi-z usb d? signal (see section 5.3.1). 17 10 19 gnd gnd ground . 18 11 20 v cc pwr v cc . connect to 3.3v power source. 19 12 21 gnd gnd ground . n/a n/a 22 sysirq i input active high . usb interrupt request (see section 5.3.4). tie to gnd if functionality is not used. n/a n/a 23 24 25 gnd gnd ground . 20 13 [3] 26 [3] pwr500# [2] ( pu 10k ) i/o active low . vbus power granted indicator used in bus-powered designs (see section 5.3.11). alternate function for 68320. 21 14 27 gnd ( reserved ) reserved . tie to gnd. notes: 1. if byte 8, bit 4 of the eeprom is set to ?0?, the ata interface pins are only active when vbus_ata_en is asserted. see sectio n 5.3.9. 2. a ?#? sign after the pin name indicates that it is active low. 3. the general purpose inputs can be enabled on atapuen, pwr500#, and drvpwrvld via eeprom byte 8, bit 7 on cy7c68320/cy7c68321.
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 8 of 36 n/a n/a 28 nc no connect . 22 15 29 scl o active for several ms at start-up. clock signal for i 2 c interface (see section 5.3.2). 23 16 30 sda i/o data signal for i 2 c interface (see section 5.3.2). n/a n/a 31 32 nc no connect . 24 17 33 v cc pwr v cc . connect to 3.3v power source. 25 18 34 dd0 i/o [1] hi-z ata data bit 0 . 26 19 35 dd1 i/o [1] hi-z ata data bit 1 . 27 20 36 dd2 i/o [1] hi-z ata data bit 2 . 28 21 37 dd3 i/o [1] hi-z ata data bit 3 . n/a n/a 38 v cc pwr v cc . connect to 3.3v power source. n/a n/a 39 gnd gnd ground . n/a n/a 40 nc nc no connect . n/a n/a 41 gnd ground . n/a n/a 42 nc nc no connect . n/a n/a 43 gnd ground . 29 22 44 dd4 i/o [1] hi-z ata data bit 4 . 30 23 45 dd5 i/o [1] hi-z ata data bit 5 . 31 24 46 dd6 i/o [1] hi-z ata data bit 6 . 32 25 47 dd7 i/o [1] hi-z ata data bit 7 . 33 26 48 gnd gnd ground . 34 27 49 v cc pwr v cc . connect to 3.3v power source. 35 28 50 gnd gnd ground . n/a n/a 51 52 nc nc no connect . n/a n/a 53 v cc pwr v cc . connect to 3.3v power source. 36 29 54 diow# [2] o/z [1] driven high (cmos) ata control . 37 30 55 dior# o/z [1] driven high (cmos) ata control . 38 31 56 dmack# o/z [1] driven high (cmos) ata control . n/a n/a 57 nc nc no connect . n/a n/a 58 lowpwr# o usb suspend indicator (see section 5.3.7). ?0? = chip active. vbus power draw governed by pwr500# pin. ?hi-z? = chip suspend. vbus system current limited to usb suspend mode value. n/a n/a 59 60 61 nc nc no connect. n/a n/a 62 vbuspwrd i input bus-powered operation selector . used in systems that are capable of being bus or self-powered to indicate the current power mode. n/a n/a 63 64 nc nc no connect . n/a n/a 65 gnd gnd ground . table 5-1. at2lp pin descriptions note: (italics pin names denote pin functionality during cy7c68300a-compatibility mode) (continued) 56 ssop 56 qfn 100 tqfp pin name pin type default state at start-up pin description
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 9 of 36 39 32 66 v cc pwr v cc . connect to 3.3v power source. 40 33 67 intrq i [1] input ata interrupt request . 41 34 68 da0 o/z [1] driven high after 2 ms delay ata address . 42 35 69 da1 o/z [1] driven high after 2 ms delay ata address . 43 36 [3] 70 [3] drvpwrvld ( da2 ) i input device presence detect (see section 5.3.5). config- urable polarity, controlled by eeprom address 0x08. this pin must be connected to gnd if functionality is not utilized. alternate function : input when the eeprom config- uration byte 8 has bit 7 set to one. the input value is reported through ep1in (byte 0, bit 0). 44 37 71 cs0# o/z [1] driven high after 2 ms delay ata chip select . 45 38 72 cs1# o/z [1] driven high after 2 ms delay ata chip select . 46 39 73 da2 ( vbus_pwr_valid ) o/z [1] driven high after 2 ms delay ata address . 47 40 74 areset# o/z [1] ata reset . 48 41 75 gnd gnd ground . n/a n/a 76 nc nc no connect . 49 42 77 reset# i input chip reset (see section 5.3.13). this pin is normally tied to v cc through a 100k resistor, and to gnd through a 0.1-f capacitor, supplying a 10-ms reset. 50 43 78 v cc pwr v cc . connect to 3.3v power source. 51 44 79 vbus_ata_enable ( ata_en ) i input vbus detection (see section 5.3.9). indicates to the CY7C68300B/cy7c68301b that vbus power is present. 52 45 80 dd8 i/o [1] hi-z ata data bit 8 . 53 46 81 dd9 i/o [1] hi-z ata data bit 9 . 54 47 82 dd10 i/o [1] hi-z ata data bit 10 . 55 48 83 dd11 i/o [1] hi-z ata data bit 11 . n/a n/a 84 gnd ground . n/a n/a 85 v cc pwr v cc . connect to 3.3v power source. n/a n/a 86 87 nc nc no connect . n/a 36 [3] 13 [3] 54 [3] 88 89 90 91 92 93 gpio0 gpio1 gpio2_nhs gpio3 gpio4 gpio5 i/o [3] general purpose i/o pins (see section 5.3.6). the gpio pins must be tied to gnd if functionality is not utilized. if the hs_indicator config bit is set, the gpio2_nhs pin will reflect the operating speed: ?1? = full-speed operation. ?0? = high-speed operation. n/a n/a 94 gnd gnd ground . 56 49 95 dd12 i/o [1] hi-z ata data bit 12 . table 5-1. at2lp pin descriptions note: (italics pin names denote pin functionality during cy7c68300a-compatibility mode) (continued) 56 ssop 56 qfn 100 tqfp pin name pin type default state at start-up pin description
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 10 of 36 5.3 additional pin descriptions 5.3.1 dplus, dminus dplus and dminus are the usb signaling pins; they should be tied to the d+ and d? pins of the usb connector. because they operate at high frequencies, the usb signals require special consideration when designing the layout of the pcb. see section 15.0 for pcb layout recommendations. when reset# is released, the internal pull-up on d+ is controlled by vbus_ata_enable. when vbus_ata_enable is high, d+ is pulled up. 5.3.2 scl, sda the clock and data pins for the i 2 c port should be connected to the configuration eeprom and to 2.2k pull-up resistors tied to v cc . the scl and sda pins are active for several milli- seconds at start-up. 5.3.3 xtalin, xtalout the at2lp requires a 24-mhz ( 100ppm) signal to derive internal timing. typically, a 24-mhz (20-pf, 500- w, parallel- resonant fundamental mode) crystal is used, but a 24-mhz square wave from another source can also be used. if a crystal is used, connect its pins to xtalin and xtalout, and also through 12-pf capacitors to gnd as shown in figure 5-6 . if an alternate clock source is used, apply it to xtalin and leave xtalout open. 5.3.4 sysirq the sysirq pin provides a way for systems to request service from host software by using the usb interrupt pipe. if the at2lp has no pending interrupt data to return, usb interrupt pipe data requests are naked. if pending data is available, the at2lp returns 16 bits of data; this data indicates the hs_mode signal (that indicates whether at2lp is operating in high-speed or full-speed), the vbuspwrd pin, and the gpio pins. table 5-2 gives the bitmap for the data returned on the interrupt pipe and figure 5-7 depicts the latching algorithm incorporated by at2lp. the sysirq pin must be tied low if the hid function is used (refer to section 6.0 ). 24mhz xtal 12pf xtalin xtalout 12pf figure 5-6. xtalin / xtalout diagram table 5-2. usb interrupt pipe data bitmap usb interrupt data byte 1 usb interrupt data byte 0 7654321076543210 reserved reserved reserved reserved reserved reserved usb high-speed vbuspwrd reserved reserved gpio[5] gpio[4] gpio[3] gpio[2] gpio[1] gpio[0]
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 11 of 36 5.3.5 drvpwrvld when this pin is enabled via eeprom byte 8, bit 0, the at2lp will inform the host that a removable device, such as a cf card, is present. the CY7C68300B/cy7c68301b will use drvpwrvld to detect that the removable device is present. pin polarity is controlled by bit 1 of eeprom address 8. when drvpwrvld is deasserted, the at2lp will report a ?no media present? status (asc = 0x3a, asq = 0x00) to the host. when the media has been detected again, the at2lp will report a ?media changed? status to the host (asc = 0x28, asq = 0x00). when a removable device is used, it is always the master device. only one removable device may be attached to the at2lp. if the system only contains a removable device, eeprom byte 8, bit 6 must be set to ?0? to disable ata device detection at start-up. if a non-removable device is connected in addition to a removable media device, it must be configured as a slave (device address 1). drvpwrvld can also be configured as an input. see section 6.0 hid functions for button controls . 5.3.6 gpio pins the gpio pins allow for a general purpose input/output interface. there are several different interfaces to the gpio pins: configuration bytes 0x09 and 0x0a contain the default set- tings for the gpio pins. the host can modify the settings of the gpio pins during operation. this is done with vendor-specific commands de- scribed in section 8.6. the status of the gpio pins is also returned on the interrupt endpoint (ep1) in response to a sysirq. see section for sysirq details. gpio2_nhs also has an alternate function. if the ?hs indicator enable? configuration (bit 2 of eeprom address 8) is set, the gpio2_nhs pin will reflect the operating speed of the device (full- or high-speed usb). 5.3.7 lowpwr# lowpwr# is an output pin that is driven to ?0? when the at2lp is active. lowpwr# is placed in hi-z when the at2lp is in a suspend state. 5.3.8 ata interface pins design practices for signal integrity as outlined in the ata/atapi-6 specification should be followed with systems that utilize a ribbon cable interconnect between the CY7C68300B/cy7c68301b?s ata interface and the attached ata/atapi device, especially if ultra dma mode is utilized. 5.3.9 vbus_ata_enable vbus_ata_enable is typically used to indicate to the at2lp that power is present on vbus. this pin is polled by the at2lp at start-up and then every 20ms thereafter. if this pin is ?1?, the internal 1.5k pull-up is attached to d+. if this pin is ?0?, the at2lp will release the pull-up on d+ as required by the usb specification. also, if eeprom byte 8, bit 4 is ?0?, the ata interface pins will be placed in a high impedance (hi-z) state when vbus_ata_enable is ?0?. if eeprom byte 8, bit 4 is ?1?, the ata interface pins will still be driven when vbus_ata_enable is ?0?. usb interrupt pipe polled? yes no nak request sysirq=1? latch state of io pins set int_data = 1 int_data = 1? no return interrupt data set int_data = 0 yes yes no yes int_data = 0 and sysirq=0? no figure 5-7. sysirq latching algorithm
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 12 of 36 5.3.10 atapuen this output controls the required host pull-up resistors on the ata interface. atapuen is driven to ?0? when the ata bus is inactive. atapuen is driven to ?1? when the ata bus is active. atapuen is set to a hi-z state along with all other ata interface pins if vbus_ata_enable is deasserted and the ata_en functionality (eeprom byte 8, bit 4) is enabled. atapuen can also be configured as an input. see section 6.0 hid functions for button controls 5.3.11 pwr500# the at2lp asserts pwr500# to indicate that vbus current may be drawn up to the limit specified by the bmaxpower field of the usb configuration descriptors. in the 100-pin package, pwr500# w ill only be asserted if vbuspwrd and drvpwrvld are also asserted. in the 56-pin package, pwr500# only functions during bus-powered operation. if the at2lp enters a low-power state, pwr500# is deasserted. when normal operation is resumed, pwr500# is restored accordingly. naturally, the pwr500# pin should never be used to control power sources for the at2lp. in the 68320 parts, pwr500# can also be configured as an input. if the drive power valid enable bit is set (eeprom byte 8, bit 1), pwr500# will only be driven when drive power valid is active. see section 6.0 hid functions for button controls . 5.3.12 vbuspwrd some devices have the ability to be either self-powered or bus-powered. the vbuspwrd input pin enables these devices to change between self-powered to bus-powered modes by changing the contents of the bmaxpower field and the self-powered bit in the configuration descriptor. note that current host drivers do not poll the device for this information, so this pin is only effective on a usb or power-up reset. 5.3.13 reset# asserting reset# for 10 ms will reset the entire chip. this pin is normally tied to v cc through a 100k resistor, and to gnd through a 0.1- f capacitor, as shown in the figure below. cypress does not recommend an rc reset circuit for bus- powered devices. see the application note ez-usb fx2 ? /at2 ? /sx2 ? reset and power considerations at www.cypress.com for more information. 6.0 hid functions for button controls cypress? cy7c68320/cy7c68321 introduces the capability to support human interface device (hid) signaling to the host for such functions as buttons. the ability to add buttons to a mass storage solution opens new applications for backup and other device-side notification to the host. optional hid functions can be added to the eeprom descriptors by setting bit 7 of byte 8 of the eeprom to a value of ?1?. when this bit is set, several pins adopt alternate functions for the 56-pin package. this allows the pins to be used as button inputs. if there is a hid descriptor in the eeprom, these pins are polled by the hardware approxi- mately every 17 ms. if a change is detected in the pin(s) state, a report is sent via ep1. the report format for byte 0 and byte 1 are shown in table 6-1 . table 5-3. bus-power description vbuspwrd value 1 0 not present (56-pin) pwr500# 1 when config = 0 0 when config = 1 1 1 when config = 0 0 when config = 1 bmaxpower 250 (500ma) 1 (2ma) eeprom value used bmattributes bit 6 0 1 eeprom value used figure 5-8. typical reset circuit 100k ? ? ? ? 0.1 f reset# table 6-1. ep1 data bitmap ep1 data byte 1 ep1 data byte 0 7654321076543210 reserved reserved reserved reserved reserved reserved usb high-speed vbuspwrd drvpwrvld gpio[4] gpio[3] gpio[2] gpio[1] gpio[0] atapuen pwr500#
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 13 of 36 7.0 functional overview 7.1 usb signaling speed at2lp operates at the following two of the three rates defined in the usb specification revision 2.0 dated april 27, 2000: full-speed, with a signaling bit rate of 12 mbits/sec high-speed, with a signaling bit rate of 480 mbits/sec. at2lp does not support the low-speed signaling rate of 1.5 mbits/sec. 7.2 ata interface the ata/atapi port on the at2lp is compatible with the infor- mation technology?at attachment with packet interface?6 (ata/atapi-6) specification, t13/1410d rev 2a . the at2lp supports both atapi packet commands as well as ata commands (by use of ata command blocks), as outlined in section . refer to the usb mass storage class (msc) bulk only transport (bot) specification for information on command block formatting. additionally, the at2lp translates atapi sff-8070i commands to ata commands for seamless integration of ata devices with generic mass storage class bot drivers. 7.2.1 ata command block (atacb) the ata command block (atacb) functionality provides a means of passing ata commands and ata register accesses to the attached device for execution. atacb commands are transferred in the command block wrapper command block (cbwcb) portion of the command block wrapper (cbw). the atacb is distinguished from other command blocks by having the first two bytes of the command block match the bvscbsignature and bvscbsubcommand values that are defined in table 7-1 . only command blocks that have a valid bvscbsignature and bvscbsubcommand are interpreted as ata command blocks. all other fields of the cbw and restrictions on the cbwcb remain as defined in the usb mass storage class bulk-only transport specification. the atacb must be 16 bytes in length. the following table and text defines the fields of the atacb. table 7-1. atacb field descriptions byte field name field description 0 bvscbsignature this field indicates to the CY7C68300B/cy7c68301b that the atacb contains a vendor-specific command block. this value of this field must match the value in eeprom address 0x04 for this vendor-specific command to be recognized. 1 bvscbsubcommand this field must be set to 0x24 for atacb commands. 2 bmatacbactionselect this field controls the execution of the atacb according to the bitfield values: bit 7 identifypacketdevice ? this bit indicates that the data phase of the command will contain atapi (0xa1) or ata (0xec) identify device data. setting identifypacketdevice when the data phase does not contain identify device data will result in unspecified device behavior. 0 = data phase does not contain identify device data 1 = data phase contains atapi or ata identify device data bit 6 udmacommand ? this bit enables supported udma device transfers. setting this bit when a non-udma capable device is attached w ill result in undetermined behavior. 0 = do not use udma device transfers (only use pio mode) 1 = use udma device transfers bit 5 devoverride ? this bit determines whether the dev bit value is taken from the value assigned to the lun during start-up or from the atacb. 0 = the dev bit will be taken from the value assigned to the lun during start-up 1 = the dev bit will be taken from the atacb field 0x0b, bit 4 bit 4 derroroverride ? this bit controls the device error override feature. this bit should not be set during a bmatacbactionselect taskfileread. 0 = data accesses are halted if a device error is detected 1 = data accesses are not halted if a device error is detected bit 3 perroroverride ? this bit controls the phase error override feature. this bit should not be set during a bmatacbactionselect taskfileread. 0 = data accesses are halted if a phase error is detected 1 = data accesses are not halted if a phase error is detected bit 2 pollaltstatoverride ? this bit determines whether or not the alternate status register will be polled and the bsy bit will be used to qualify the atacb operation. 0 = the altstat register will be polled until bsy=0 before proceeding with the atacb operation 1 = the atacb operation will be executed without polling the altstat register.
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 14 of 36 bit 1 deviceselectionoverride ? this bit determines when the device selection will be performed in relation to the command register write accesses. 0 = device selection will be performed prior to command register write accesses 1 = device selection will be performed following command register write accesses bit 0 taskfileread ? this bit determines whether or not the taskfile register data selected in bmatacbregisterselect is returned. if this bit is set, the dcbwdatatransferlength field must be set to 8. 0 = execute atacb command and data transfer (if any) 1 = only read taskfile registers selected in bmatacbregisterselect and return 0x00h for all others. the format of the 12 bytes of returned data is as follows: address offset 0x00 (0x3f6) ? alternate status address offset 0x01 (0x1f1) ? features / error address offset 0x02 (0x1f2) ? sector count address offset 0x03 (0x1f3) ? sector number address offset 0x04 (0x1f4) ? cylinder low address offset 0x05 (0x1f5) ? cylinder high address offset 0x06 (0x1f6) ? device / head address offset 0x07 (0x1f7) ? command / status 3 bmatacbregisterselect this field controls which of the taskfile register read or write accesses occur. taskfile read data w ill always be 8 bytes in l ength, and unselected register data will be returned as 0x00. register accesses occur in sequential order as outlined below (0 to 7). bit 0 (0x3f6) device control / alternate status bit 1 (0x1f1) features / error bit 2 (0x1f2) sector count bit 3 (0x1f3) sector number bit 4 (0x1f4) cylinder low bit 5 (0x1f5) cylinder high bit 6 (0x1f6) device / head bit 7 (0x1f7) command / status 4 batacbtransferblockcount this value indicates the maximum requested block size in 512-byte incre- ments. this value must be set to the last value used for the ?sectors per block? in the set_multiple_mode command. legal values are 0, 1, 2, 4, 8, 16, 32, 64, and 128 where 0 indicates 256 sectors per block. a command failed status will be returned if an illegal value is used in the atacb. 5?12 batacbtaskfilewritedata these bytes contain ata register data used with ata command or pio write operations. only registers selected in bmatacbregisterselect are required to hold valid data when accessed. the registers are as follows. atacb address offset 0x05 (0x3f6) ? device control atacb address offset 0x06 (0x1f1) ? features atacb address offset 0x07 (0x1f2) ? sector count atacb address offset 0x08 (0x1f3) ? sector number atacb address offset 0x09 (0x1f4) ? cylinder low atacb address offset 0x0a (0x1f5) ? cylinder high atacb address offset 0x0b (0x1f6) ? device atacb address offset 0x0c (0x1f7) ? command 13?15 reserved these bytes must be set to 0x00 for atacb commands. table 7-1. atacb field descriptions (continued) byte field name field description
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 15 of 36 8.0 operating modes 8.1 operational mode selection flow during the power-up sequence, the at2lp checks the i 2 c port for an eeprom and checks to see if the ata connector is configured for board manufacturing test mode. at2lp then selects an operating mode as shown below. if an i 2 c eeprom with a 0x4d4d signature is found, the CY7C68300B/cy7c68301b uses the same pinout and ee- prom format as the cy7c68300a (ez-usb at2). if the first two bytes of the eeprom contain 0x534b the at2lp uses the values stored in the eeprom to configure the usb descriptors for normal operation. if no eeprom is detected, the at2lp uses a vid/pid of 0x00/0x00. this is not a valid mode of operation. if an invalid eeprom signature is read, the at2lp defaults into board manufacturing test mode. there is an additional method available to put the at2lp into board manufacturing test mode to allow reprogramming of read eeprom eeprom found? eeprom signature 0x4d4d? eeprom signature 0x534b? ata enable pin high? yes no yes yes no set ez-usb at2+ (cy7c68300a) pinout no set ez-usb at2lp pinout no areset# low? yes yes no normal mass storage mode board manufacturing test mode "no eeprom detected" mode figure 8-1. operational mode selection
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 16 of 36 eeproms without an ata/atapi device attached. if the ata reset (areset#) line is low on power-up, the at2lp will enter board manufacturing test mode. a convenient way to pull the areset# line low is to short pins 1 and 3 on the ata connector, which will tie the areset# line to the pull-down on dd7. 8.2 ?no eeprom detected? mode when no eeprom is detected at start-up, the at2lp will enumerate with vid/pid/did values that are all 0x00, which is not a valid mode of operation. these values can be factory programmed into the at2lp for high-volume applications to avoid the need for an external eeprom in some designs. contact your local cypress semiconductor sales office for details. 8.3 normal mass storage mode in normal mass storage mode, the chip behaves as a usb 2.0 to ata/atapi bridge. this includes all typical usb device states (powered, configured, etc.). the usb descriptors are returned according to the values stored in the external eeprom. an external eeprom is required for mass storage class bulk-only transport compliance, since a unique serial number is required for each device. also, cypress requires customers to use their own vendor and product ids for final products. 8.4 board manufacturing test mode in board manufacturing test mode, the chip behaves as a usb 2.0 device but the ata/atapi interface is not fully active. in this mode, the at2lp allows for reading from and writing to the eeprom, and for board level testing through vendor specific atapi commands utilizing the cbw command block as described in the usb mass storage class bulk-only transport specification . there is a vendor-specific atapi command for the eeprom access (cfgcb) and one for the board level testing (mfgcb). 8.4.1 cfgcb the cfg_load and cfg_read vendor-specific commands are passed down through the bulk pipe in the cbwcb portion of the cbw. the format of this cfgcb is shown below. byte 0 will be a vendor-specific command designator whose value is configurable and set in the configuration data (eeprom address 0x04). byte 1 must be set to 0x26 to identify cfgcb. byte 2 is reserved and must be set to zero. byte 3 is used to determine the memory source to write/read. for the CY7C68300B/cy7c68301b, this byte must be set to 0x02, indicating the eeprom is present. bytes 4 and 5 are used to determine the start address. for the CY7C68300B/301b, this must always be 0x0000. bytes 6 through 15 are reserved and must be set to zero. the data transferred to the eeprom must be in the format specified in table 8-6 of this data sheet. maximum data transfer size is 255 bytes. the data transfer length is determined by the cbw data transfer length specified in bytes 8 through 11 (dcbwdatatransferlength) of the cbw (refer to table 8-1 ). the type/direction of the command will be determined by the direction bit specified in byte 12, bit 7 (bmcbwflags) of the cbw (refer to table 8-1 ). table 8-1. command block wrapper bits offset76543210 0?3 dcbwsignature 4?7 dcbwtag 8?11 (08h?0bh) dcbwdatatransferlength 12 (0ch) bwcbwflags dir obsolete reserved (0) 13 (0dh) reserved (0) bcbwlun 14 (0eh) reserved (0) bcbwcblength 15?30 (0fh1eh) cbwcb (cfgcb or mfgcb) table 8-2. example cfgcb offset cfgcb byte descriptions bits 76543210 0 bvscbsignature (set in configuration bytes) 0 0 1 0 0 1 0 0 1 bvscbsubcommand (must be 0x26) 0 0 1 0 0 1 1 0 2 reserved (must be set to zero) 0 0 0 0 0 0 0 0 3 data source (must be set to 0x02) 0 0 0 0 0 0 1 0 4 start address (lsb) (must be set to zero) 0 0 0 0 0 0 0 0 5 start address (msb) (must be set to zero) 0 0 0 0 0 0 0 0 6?15 reserved (must be set to zero) 0 0 0 0 0 0 0 0
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 17 of 36 8.4.2 mfgcb the mfg_load and mfg_read vendor-specific commands will be passed down through the bulk pipe in the cbwcb portion of the cbw. the format of this mfgcb is shown below. byte 0 is a vendor-specific command designator whose value is configurable and set in the configuration data. byte 1 must be 0x27 to identify mfgcb. byte 2?15 are reserved and must be set to zero. the data transfer length will be determined by the cbw data transfer length specified in bytes 8 through 11 (dcbwdatatransferlength) of the cbw. the type/direction of the command is determined by the direction bit specified in byte 12, bit 7 (bmcbwflags) of the cbw. 8.4.2.1 mfg_load during a mfg_load, the CY7C68300B/cy7c68301b goes into manufacturing test mode. manufacturing test mode is provided as a means to implement board or system level inter- connect tests. during manufacturing test mode operation, all outputs not directly associated with usb operation are control- lable. normal control of the output pins are disabled. control of the select at2lp io pins and their three-state controls are mapped to the atapi data packet associated with this request. (see table 8-4 for an explanation of the required mfg_load data format.) this requires a write of seven bytes. to exit manufacturing test mode, a hard reset (reset#) is required. 8.4.2.2 mfg_read this usb request returns a ?snapshot in time? of select at2lp input pins. at2lp input pins not directly associated with usb operation, can be sampled at any time during manufacturing test mode operation. see table 8-5 for an explanation of the mfg_read data format. the data length shall always be eight bytes. table 8-3. example mfgcb offset mfgcb byte description bits 76543210 0 0 bvscbsignature (set in configuration bytes) 00100100 1 1 bvscbsubcommand (hardcoded 0x27) 00100111 2?15 2?15 reserved (must be zero) 0 0 0 0 0 0 0 0 table 8-4. mfg_load data format byte bit(s) function 0 7 areset# 6 reserved 5:4 cs#[1:0] 3:1 da[2:0] 0 reserved 1 7 dd[15:0] three-state (0 = hi-z all dd pins, 1 = drive dd pins). 3:6 reserved 2dmack# 1dior# 0diow# 2 7:0 dd[7:0] 3 7:0 dd[15:8] 47:6reserved 5:0 gpio output enable [5:0] 57:6reserved 5:0 gpio output data [5:0] 67:0reserved table 8-5. mfg_read data format byte bit(s) data 0 7 areset# (output value only) 6 vbus_ata_enable 5:1 reserved. this data should be ignored. 0 intrq 1 7 dd[15:0] three-state 6 reserved. this data should be ignored. 5 reserved. this data should be ignored. 4dmarq 1 3 iordy 2:0 reserved. this data should be ignored. 2 7:0 dd[7:0] 3 7:0 dd[15:8] 47:6reserved 5:0 gpio output enable [5:0] 57:6reserved 5:0 gpio output data [5:0] 6 7:0 reserved. this data should be ignored. 7 7:0 reserved. this data should be ignored. table 8-4. mfg_load data format (continued) byte bit(s) function
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 18 of 36 8.5 eeprom organization the contents of the 256-byte (2048-bit) i 2 c eeprom are arranged as follows. in table 8-6 , the column labeled ?required contents? contains the values that must be used for proper operation of the at2lp. the column labeled ?suggested contents? contains suggested values for the bytes that are defined by the customer. some values, such as the vendor id, product id and device serial number, must be customized to meet usb compliance. the ?at2lp blaster? tool on the cy4615b cd can be used to edit and program these values into an at2lp-based product (refer to figure 8-2 ). the ?at2lp primer? tool can be used to program at2lp-based products in a manufacturing environment. see section 8.4 for details on how to use vendor-specific atapi commands to read and program the eeprom. the address pins on the serial eeprom must be set such that the eeprom is at address 2 (a0=0, a1=1, a2=0) or address 4 (a0=0, a1=0, a2=1) for memories that are internally byte- addressed memories. note: devices running in backward compatibility mode should use the 68300a eeprom organization, and not the 68300b/301b/320/321 format shown in this document. figure 8-2. ?at2lp blaster? tool screen
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 19 of 36 table 8-6. eeprom organization eeprom address field name field description required contents suggested contents at2lp configuration 0x00 i 2 c eeprom signature byte 0 i 2 c eeprom signature byte 0. this byte must be 0x53. for cy7c68300a compatib ility m ode, these bytes should be set to 0x4d4d. 0x53 0x01 i 2 c eeprom signature byte 1 i 2 c eeprom signature byte 1. this byte must be 0x4b 0x4b 0x02 apm value ata device automatic power management value. if an attached ata device supports apm and this field contains other than 0x00, the at2lp will issue a set_features command to enable apm with this value during the drive initialization process. setting apm value to 0x00 disables this functionality. this value is ignored with atapi devices. 0x00 0x03 unused 0x80 0x04 bvscbsignature value value in the first byte of the cbw cb field that designates that the cb is to be decoded as vendor specific ata commands instead of the atapi command block. see section 7.0 for more detail on how this byte is used. 0x24 0x05 reserved bits (7:6) 0x07 enable mode page 8 bit (5) set to 1 to enable the write caching mode page (page 8). if this page is enabled, windows will disable write caching by default which will limit write performance. disable wait for intrq bit (4) set to 1 to poll status register rather than waiting for intrq. setting this bit to 1 will improve usb bot test results but may introduce compatibility problems with some devices. busy bit delay bit (3) enables a delay of up to 120 ms at each read of the drq bit where the device data length does not match the host data length. this allows the CY7C68300B/cy7c68301b to work with most devices that incorrectly clear the busy bit before a valid status is present. short packet before stall bit (2) determines if a short packet is sent prior to the stall of an in endpoint. the usb mass storage class bulk-only speci- fication allows a device to send a short or zero-length in packet prior to returning a stall handshake for certain cases. certain host controller drivers may require a short packet prior to stall. 1 = force a short packet before stall. 0 = don?t force a short packet before stall. srst enable bit (1) determines if the at2lp is to do an srst reset during drive initialization. at least one reset must be enabled. do not set srst to 0 and skip pin reset to 1 at the same time. 1 = perform srst during initialization. 0 = don?t perform srst during initialization. skip pin reset bit (0) skip areset# assertion. when this bit is set, the at2lp will bypass areset# during any initialization other than power up. do not set srst to 0 and skip pin reset to 1 at the same time. 0 = allow areset# assertion for all resets. 1 = disable areset# assertion except for power-on reset cycles.
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 20 of 36 0x06 ata udma enable bit (7) enable ultra dma data transfer support for atapi devices. if enabled, and if the atapi device reports udma support for the indicated modes, the at2lp will utilize udma data transfers at the highest negotiated rate possible. 0 = disable ata device udma support. 1 = enable ata device udma support. 0xd4 atapi udma enable bit (6) enable ultra dma data transfer support for atapi devices. if enabled, and if the atapi device reports udma support for the indicated modes, the at2lp will utilize udma data transfers at the highest negotiated rate possible. 0 = disable atapi device udma support. 1 = enable atapi device udma support. udma modes bit (5:0) these bits select which udma modes, if supported, are enabled. setting to 1 enables. multiple bits may be set. the at2lp will operate in the highest enabled udma mode supported by the device. the at2lp supports udma modes 2, 3, and 4 only. bit descriptions 5 reserved. must be set to 0. 4 enable udma mode 4. 3 reserved. must be set to 0. 2 enable udma mode 2. 1 reserved. must be set to 0. 0 reserved. must be set to 0. 0x07 reserved multiword dma mode pio modes bits(7:3) must be set to 0. bit (2) this bit selects multi-word dma. if this bit is set and the drive supports it, multi-word dma is used. bits(1:0) these bits select which pio modes, if supported, are enabled. setting to 1 enables. multiple bits may be set. the at2lp will operate in the highest enabled pio mode supported by the device. the at2lp supports pio modes 0, 3, and 4 only. pio mode 0 is always enabled by internal logic. bit descriptions 1 enable pio mode 4. 0 enable pio mode 3. 0x07 0x08 pin configurations 0x78 button_mode bit (7) button mode. set this bit to 1 to enable atapuen, pwr500# and drvpwrvld to become button inputs returned on bits 2, 1, and 0 of ep1in search_ata_bus bit (6) enables a search performed at reset to detect non- removable ata and atapi devices. systems with only a removable device (like cf readers) will set this bit to 0. systems with one removable device and one non- removable device will set this bit to 1. big_package bit (5) package select. set this bit to 1 when using the 100-pin device. table 8-6. eeprom organization (continued) eeprom address field name field description required contents suggested contents
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 21 of 36 ata_en bit (4) ata sharing enable. allows ata bus sharing with other host devices. if ata_en=1 the ata interface will be driven when vbus_ata_enable is low. if ata_en=0 the ata interface will be placed into hi-z state wh enever vbus_ata_enable is low. ?0? = ata signals hi-z when vbus_ata_enable is low. ?1? = ata signals driven when vbus_ata_enable is low. diskrdy polarity bit (3) diskrdy active polarity. ?0? = active low polarity. ?1? = active high polarity. hs indicator enable bit (2) enables gpio2_nhs pin to indicate the current operating speed of the device (if output is enabled). ?0? = normal gpio operation. ?1? = high-speed indicator enable. drive power valid polarity bit (1) controls the polarity of drvpwrvld pin ?0? = active low (?connector ground? indication) ?1? = active high (power indication from device) drive power valid enable bit (0) enable for the drvpwrvld pin. when this pin is enabled, the at2lp will enumerate a removable ide device (normally compactflash) as the master device. ?0? = pin disabled (most systems) ?1? = pin enabled (compactflash systems) 0x09 reserved general purpose io pin output enable bits (7:6) must be set to zero. bits (5:0) gpio[5:0] hi-z control. ?0? = output enabled (gpio pin is an output). ?1? = hi-z (gpio pin is an input). 0x00 0x0a reserved general purpose io pin data bits (7:6) must be set to zero. bits (5:0) if the output enable bit is set, these bits select the value driven on the gpio pins. 0x00 0x0b identify device string pointer lun0 if this value is 00, the identify device data will be taken from the device. if this string is non-zero, it is used as a pointer to a 24 byte ascii (non-unicode) string in the eeprom. this string will be used as the device identifier. this string is used by many operating systems as the user-visible name for the device. 0x00 0x0c identify device string pointer lun1 0x00 0x0d delay after reset number of 20-ms ticks to wait between reset and attempting to access the drive. 0x00 0x0e reserved bits (7:4) 0x00 enable cf udma bit (3) ?1? = allow udma to be used with removable-media devices ?0? = udma will not be used with removable-media devices some cf devices will interfere with udma if the udma lines are connected to them. this bit tells the at2lp if the udma lines are connected to the removable-media device. fixed number of logical units = 2 bit (2) if bits 1 and 2 are both 0, the number of logical units will be determined by searching the ata and cf buses for devices. table 8-6. eeprom organization (continued) eeprom address field name field description required contents suggested contents
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 22 of 36 fixed number of logical units = 1 bit (1) if bits 1 and 2 are both 0, the number of logical units will be determined by searching the ata and cf buses for devices. search ata on vbus removed bit (0) search for ata devices when vbus returns. if this bit is set, the ata bus will be searched for ata devices every time at2lp is plugged into a computer. 0x0f reserved must be set to 0x00. 0x00 device descriptor 0x10 blength length of device descriptor in bytes. 0x12 0x11 bdescriptor type descriptor type. 0x01 0x12 bcdusb (lsb) usb specification release number in bcd. 0x00 0x13 bcdusb (msb) 0x02 0x14 bdeviceclass device class. 0x00 0x15 bdevicesubclass device subclass. 0x00 0x16 bdeviceprotocol device protocol. 0x00 0x17 bmaxpacketsize0 usb packet size supported for default pipe. 0x40 0x18 idvendor (lsb) vendor id. cypress?s vendor id may only be used for evalu- ation purposes, and not in released products. your vendor id 0x19 idvendor (msb) 0x1a idproduct (lsb) product id. your product id 0x1b idproduct (msb) 0x1c bcddevice (lsb) device release number in bcd lsb (product release number). your release number 0x1d bcddevice (msb) device release number in bcd msb (silicon release number). 0x1e imanufacturer index to manufacturer string. this entry must equal half of the address value where the string starts or 0x00 if the string does not exist. 0x53 0x1f iproduct index to product string. this entry must equal half of the address value where the string starts or 0x00 if the string does not exist. 0x69 0x20 iserialnumber index to serial number string. this entry must equal half of the address value where the string starts or 0x00 if the string does not exist. the usb mass storage class bulk-only transport specification requires a unique serial number (in upper case, hexadecimal characters) for each device. 0x75 0x21 bnumconfigurations number of configurations supported. 1 for mass storage: 2 for hid: 3 for csm 0x03 device qualifier 0x22 blength length of device descriptor in bytes. 0x0a 0x23 bdescriptor type descriptor type. 0x06 0x24 bcdusb (lsb) usb specification release number in bcd. 0x00 0x25 bcdusb (msb) usb specification release number in bcd. 0x02 0x26 bdeviceclass device class. 0x00 0x27 bdevicesubclass device subclass. 0x00 0x28 bdeviceprotocol device protocol. 0x00 0x29 bmaxpacketsize0 usb packet size supported for default pipe. 0x40 0x2a bnumconfigurations number of configurations supported. 0x01 table 8-6. eeprom organization (continued) eeprom address field name field description required contents suggested contents
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 23 of 36 0x2b breserved reserved for future use. must be set to zero. 0x00 configuration descriptor 0x2c blength length of configuration descriptor in bytes. 0x09 0x2d bdescriptortype descriptor type. 0x02 0x2e btotallength (lsb) number of bytes returned in this configuration. this includes the configuration descriptor plus all the interface and endpoint descriptors. 0x20 0x2f btotallength (msb) 0x00 0x30 bnuminterfaces number of interfaces supported. 0x01 0x31 bconfiguration value the value to use as an argument to set configuration to select the configuration. this value must be set to 0x01. 0x01 0x32 iconfiguration index to the configuration string. this entry must equal half of the address value where the string starts, or 0x00 if the string does not exist. 0x00 0x33 bmattributes device attributes for this configuration. bit (7) reserved. must be set to 1. bit (6) self-powered. must be set to 1. bit (5) remote wake-up. must be set to 0. bits (4?0) reserved. must be set to 0. 0xc0 0x34 bmaxpower maximum power consumption for this configuration. units used are ma*2 (i.e., 0x31 = 98 ma, 0xf9 = 498 ma). 0x00 reported for self-powered devices. note: a value of 0x00 or 0x01 results in the 56-pin package configuring itself for self-powered mode, whereas a value greater than 0x01 results in the 56-pin package reporting itself as bus-powered. this is regardless of what address 0x33 is set to reflect in the 56-pin package. 0x01 interface and endpoint descriptors interface descriptor 0x35 blength length of interface descriptor in bytes. 0x09 0x36 bdescriptortype descriptor type. 0x04 0x37 binterfacenumber interface number. 0x00 0x38 balternatesetting alternate setting. 0x00 0x39 bnumendpoints number of endpoints. 0x02 0x3a binterfaceclass interface class. 0x08 0x3b binterfacesubclass interface subclass. 0x06 0x3c binterfaceprotocol interface protocol. 0x50 0x3d iinterface index to first interface string. this entry must equal half of the address value where the string starts or 0x00 if the string does not exist. 0x00 usb bulk out endpoint 0x3e blength length of this descriptor in bytes. 0x07 0x3f bdescriptortype endpoint descriptor type. 0x05 0x40 bendpointaddress this is an out endpoint, endpoint number 2. 0x02 0x41 bmattributes this is a bulk endpoint. 0x02 0x42 wmaxpacketsize (lsb) max data transfer size. to be set by speed (full speed 0x0040; high speed 0x0200) 0x00 0x43 wmaxpacketsize (msb) 0x02 0x44 binterval high-speed interval for polling (maximum nak rate). set to zero for full speed. 0x00 table 8-6. eeprom organization (continued) eeprom address field name field description required contents suggested contents
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 24 of 36 usb bulk in endpoint 0x45 blength length of this descriptor in bytes. 0x07 0x46 bdescriptortype endpoint descriptor type. 0x05 0x47 bendpointaddress this is an in endpoint, endpoint number 8. 0x88 0x48 bmattributes this is a bulk endpoint. 0x02 0x49 wmaxpacketsize (lsb) max data transfer size. automatically set by at2 (full speed 0x0040; high speed 0x0200) 0x00 0x4a wmaxpacketsize (msb) 0x02 0x4b binterval high-speed interval for polling (maximum nak rate). set to zero for full speed. 0x00 (optional) hid interface descriptor 0x4c blength length of hid interface descriptor 0x09 0x4d bdescriptortypes interface descriptor type 0x04 0x4e binterfacenumber number of interfaces (2) 0x02 0x4f balternatesetting alternate setting 0x00 0x50 bnumendpoints number of endpoints used by this interface 0x01 0x51 binterfaceclass class code 0x03 0x52 binterfacesubclass sub class 0x00 0x53 binterfacesubsubclass sub sub class 0x00 0x54 iinterface index of string descriptor 0x00 usb interrupt in endpoint 0x5e blength length of this descriptor in bytes. 0x07 0x5f bdescriptortype endpoint descriptor type. 0x05 0x60 bendpointaddress this is an in endpoint, endpoint number 1. 0x81 0x61 bmattributes this is an interrupt endpoint. 0x03 0x62 wmaxpacketsize (lsb) max data transfer size. 0x02 0x63 wmaxpacketsize (msb) 0x00 0x64 binterval interval for polling (max. nak rate). 0x10 (optional) hid descriptor 0x55 blength length of hid descriptor 0x09 0x56 bdescriptortype descriptor type hid 0x21 0x57 bcdhid (lsb) hid class specification release number (1.10) 0x10 0x58 bcdhid (msb) 0x01 0x59 bcountrycode country code 0x00 0x5a bnumdescriptors number of class descriptors (1 report descriptor) 0x01 0x5b bdescriptortype descriptor type 0x22 0x5c wdescriptorlength (lsb) length of hid report descriptor 0x22 0x5d wdescriptorlength (msb) 0x00 terminator descriptors 0x65 terminator 0x00 (optional) hid report descriptor 0x66 usage_page vendor defined - ffa0 0x06 0x67 0xa0 0x68 0xff table 8-6. eeprom organization (continued) eeprom address field name field description required contents suggested contents
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 25 of 36 0x69 usage vendor defined 0x09 0x6a 0xa5 0x6b collection application 0xa1 0x6c 0x01 0x6d usage vendor defined 0x09 0x6e 0xa6 input report 0x6f usage vendor defined 0x09 0x70 0xa7 0x71 logical_minimum ?128 0x15 0x72 0x80 0x73 logical_maximum 127 0x25 0x74 0x7f 0x75 report_size 8 bits 0x75 0x76 0x08 0x77 report_count 2 fields 0x95 0x78 0x02 0x79 input input (data, variable, absolute) 0x81 0x7a 0x02 output report 0x7b usage usage - vendor defined 0x09 0x7c 0xa9 0x7d logical_minimum logical minimum (-128) 0x15 0x7e 0x80 0x7f logical_maximum logical maximum (127) 0x25 0x80 0x7f 0x81 report_size report size 8 bits 0x75 0x82 0x08 0x83 report_count report count 2 fields 0x95 0x84 0x02 0x85 output output (data, variable, absolute 0x91 0x86 0x02 0x87 end collection 0xc0 (optional) standard content security interface descriptor 0x88 blength byte length of this descriptor 0x09 0x89 bdescriptortype interface descriptor type 0x0d 0x8a binterfacenumber number of interface. 0x02 0x8b balternatesetting value used to select an alternate setting for the interface identified in prior field 0x8c bnumendpoints number of endpoints used by this interface (excluding endpoint 0) that are csm dependent 0x02 0x8d binterfaceclass 0x0d 0x8e binterfacesubclass must be set to zero 0x00 0x8f binterfaceprotocol must be set to zero 0x00 0x90 iinterface index of a string descriptor that describes this interface table 8-6. eeprom organization (continued) eeprom address field name field description required contents suggested contents
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 26 of 36 channel descriptor 0x91 blength byte length of this descriptor 0x09 0x92 bdescriptortype channel descriptor type 0x22 0x93 bchannelid number of the channel, must be a zero based value that is unique across the device 0x94 bmattributes bits(7:5) must be set to 0. 0x95 bit (4:0) 0 = not used 1 = interface 2 = endpoint 3...31 = reserved values 0x96 brecipient identifier of the target recipient if recipient type field of bmattributes = 1 then brecipient field is the binterfacenumber if recipient type field of bmattributes = 2 then brecipient field is an endpoint address, where: d7: direction (0 = out, 1 = in) d6...d4: reserved and set to zero d3...d0: endpoint number 0x97 brecipientalt alternate setting for the interface to which this channel applies 0x00 0x98 brecipientlogicalunit recipient logical unit 0x99 bmethod index of a class-specific csm descriptor that describes one of the content security methods (csm) offered by the device 0x9a bmethodvariant csm variant descriptor csm descriptor 0x9b blength byte length of this descriptor 0x06 0x9c bdescriptortype csm descriptor type 0x23 0x9d bmethodid index of a class-specific csm descriptor that describes on of the content security methods offered by the device. 0x01 0x9e icsmdescriptor index of string descriptor that describes the content security method 0x9f bcdversion (lsb) csm descriptor version number 0x10 0xa0 bcsversion (msb) 0x02 0xa1 terminator 0x00 usb string descriptor?index 0 (langid) 0xa2 blength langid string descriptor length in bytes. 0x04 0xa3 bdescriptortype descriptor type. 0x03 0xa4 langid (lsb) language supported. the CY7C68300B supports one langid value. 0x09 0xa5 langid (msb) 0x04 usb string descriptor?manufacturer 0xa6 blength string descriptor length in bytes (including blength). 0x2c 0xa7 bdescriptortype descriptor type. 0x03 0xa8 bstring unicode character lsb. ?c? 0x43 0xa9 bstring unicode character msb. 0x00 0xaa bstring unicode character lsb. ?y? 0x79 0xab bstring unicode character msb. 0x00 table 8-6. eeprom organization (continued) eeprom address field name field description required contents suggested contents
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 27 of 36 0xac bstring unicode character lsb. ?p? 0x70 0xad bstring unicode character msb. 0x00 0xae bstring unicode character lsb. ?r? 0x72 0xaf bstring unicode character msb. 0x00 0xb0 bstring unicode character lsb. ?e? 0x65 0xb1 bstring unicode character msb. 0x00 0xb2 bstring unicode character lsb. ?s? 0x73 0xb3 bstring unicode character msb. 0x00 0xb4 bstring unicode character lsb. ?s? 0x73 0xb5 bstring unicode character msb. 0x00 0xb6 bstring unicode character lsb. ? ? 0x20 0xb7 bstring unicode character msb. 0x00 0xb8 bstring unicode character lsb. ?s? 0x53 0xb9 bstring unicode character msb. 0x00 0xba bstring unicode character lsb. ?e? 0x65 0xbb bstring unicode character msb. 0x00 0xbc bstring unicode character lsb. ?m? 0x6d 0xbd bstring unicode character msb. 0x00 0xbe bstring unicode character lsb. ?i? 0x69 0xbf bstring unicode character msb. 0x00 0xc0 bstring unicode character lsb. ?c? 0x63 0xc1 bstring unicode character msb. 0x00 0xc2 bstring unicode character lsb. ?o? 0x6f 0xc3 bstring unicode character msb. 0x00 0xc4 bstring unicode character lsb. ?n? 0x6e 0xc5 bstring unicode character msb. 0x00 0xc6 bstring unicode character lsb. ?d? 0x64 0xc7 bstring unicode character msb. 0x00 0xc8 bstring unicode character lsb. ?u? 0x75 0xc9 bstring unicode character msb. 0x00 0xca bstring unicode character lsb. ?c? 0x63 0xcb bstring unicode character msb. 0x00 0xcc bstring unicode character lsb. ?t? 0x74 0xcd bstring unicode character msb. 0x00 0xce bstring unicode character lsb. ?o? 0x6f 0xcf bstring unicode character msb. 0x00 0xd0 bstring unicode character lsb. ?r? 0x72 0xd1 bstring unicode character msb. 0x00 usb string descriptor?product 0xd2 blength string descriptor length in bytes (including blength). 0x2c 0xd3 bdescriptortype descriptor type. 0x03 0xd4 bstring unicode character lsb. ?u? 0x55 0xd5 bstring unicode character msb. 0x00 0xd6 bstring unicode character lsb. ?s? 0x53 table 8-6. eeprom organization (continued) eeprom address field name field description required contents suggested contents
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 28 of 36 0xd7 bstring unicode character msb. 0x00 0xd8 bstring unicode character lsb. ?b? 0x42 0xd9 bstring unicode character msb. 0x00 0xda bstring unicode character lsb. ?2? 0x32 0xdb bstring unicode character msb. 0x00 0xdc bstring unicode character lsb. ?.? 0x2e 0xdd bstring unicode character msb. 0x00 0xde bstring unicode character lsb. ?0? 0x30 0xdf bstring unicode character msb. 0x00 0xe0 bstring unicode character lsb. ? ? 0x20 0xe1 bstring unicode character msb. 0x00 0xe2 bstring unicode character lsb. ?d? 0x53 0xe3 bstring unicode character msb. 0x00 0xe4 bstring unicode character lsb. ?i? 0x74 0xe5 bstring unicode character msb. 0x00 0xe6 bstring unicode character lsb. ?s? 0x6f 0xe7 bstring unicode character msb. 0x00 0xe8 bstring unicode character lsb. ?k? 0x72 0xe9 bstring unicode character msb. 0x00 usb string descriptor?serial number ( note : the usb mass storage class specification requires a unique serial number in each device. not providing a unique serial number can cause the operating system to crash. the serial number must be at least 12 characters, but some usb hosts will only treat the last 12 characters of the serial number as unique.) 0xea blength string descriptor length in bytes (including blength). 0x22 0xeb bdescriptor type descriptor type. 0x03 0xec bstring unicode character lsb. ?1? 0x31 0xed bstring unicode character msb. 0x00 0xee bstring unicode character lsb. ?2? 0x32 0xef bstring unicode character msb. 0x00 0xf0 bstring unicode character lsb. ?3? 0x33 0xf1 bstring unicode character msb. 0x00 0xf2 bstring unicode character lsb. ?4? 0x34 0xf3 bstring unicode character msb. 0x00 0xf4 bstring unicode character lsb. ?5? 0x35 0xf5 bstring unicode character msb. 0x00 0xf6 bstring unicode character lsb. ?6? 0x36 0xf7 bstring unicode character msb. 0x00 0xf8 bstring unicode character lsb. ?7? 0x37 0xf9 bstring unicode character msb. 0x00 0xfa bstring unicode character lsb. ?8? 0x38 0xfb bstring unicode character msb. 0x00 0xfc bstring unicode character lsb. ?9? 0x39 0xfd bstring unicode character msb. 0x00 0xfe bstring unicode character lsb. ?0? 0x30 0xff bstring unicode character msb. 0x00 table 8-6. eeprom organization (continued) eeprom address field name field description required contents suggested contents
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 29 of 36 note : more than 0x100 bytes of configuration are shown for example only. at2lp only supports 0x100 total bytes. 0x100 bstring unicode character lsb. ?a? 0x41 0x101 bstring unicode character msb. 0x00 0x102 bstring unicode character lsb. ?b? 0x42 0x103 bstring unicode character msb. 0x00 identify device string ( note : this is not a unicode string. it is the ascii string returned by the device in the identify device information. it is a fixed length (24 bytes). changing this string may cause cd authoring software to incorrectly identify the device.) 0x104 device name byte 1 ascii character ?c? 0x43 0x105 device name byte 2 ascii character ?y? 0x79 0x106 device name byte 3 ascii character ?p? 0x70 0x107 device name byte 4 ascii character ?r? 0x72 0x108 device name byte 5 ascii character ?e? 0x65 0x109 device name byte 6 ascii character ?s? 0x73 0x10a device name byte 7 ascii character ?s? 0x73 0x10b device name byte 8 ascii character ? ? 0x20 0x10c device name byte 9 ascii character ?c? 0x43 0x10d device name byte 10 ascii character ?u? 0x75 0x10e device name byte 11 ascii character ?s? 0x73 0x10f device name byte 12 ascii character ?t? 0x74 0x110 device name byte 13 ascii character ?o? 0x6f 0x111 device name byte 14 ascii character ?m? 0x6d 0x112 device name byte 15 ascii character ? ? 0x20 0x113 device name byte 16 ascii character ?n? 0x4e 0x114 device name byte 17 ascii character ?a? 0x61 0x115 device name byte 18 ascii character ?m? 0x6d 0x116 device name byte 19 ascii character ?e? 0x65 0x117 device name byte 20 ascii character ? ? 0x20 0x118 device name byte 21 ascii character ?l? 0x4c 0x119 device name byte 22 ascii character ?u? 0x55 0x11a device name byte 23 ascii character ?n? 0x4e 0x11b device name byte 24 ascii character ?0? 0x30 0x11c to 0x1ff unused rom space amount of unused rom space will vary depending on strings. 0xff table 8-6. eeprom organization (continued) eeprom address field name field description required contents suggested contents
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 30 of 36 8.6 programming the eeprom there are three methods to program the eeprom: external device programmer usb commands listed in table 8-7 in-system programming on a bed-of-nails tester. any vendor-specific usb write request to the serial rom device configuration space will simultaneously update internal configuration register values as well. if the i 2 c device is programmed without vendor specific usb commands, at2lp must be synchronously reset (reset#) before configuration data is reloaded. the at2lp supports a subset of the ?slow mode? specification (100 khz) required for 24lcxxb eeprom family device support. features such as ?multi-master,? ?clock synchroni- zation? (the scl pin is output only), ?10-bit addressing,? and ?cbus device support? are not supported. vendor-specific usb commands allow the at2lp to address up to 256 bytes of data. 8.6.1 load_config_data this request enables configuration data writes to the at2lp?s configuration space. the windex field specifies the starting address and the wlength field denotes the data length in bytes. legal values for wvalue are as follows: 0x0000 configuration bytes, address range 0x2 ? 0xf 0x0002 external i 2 c memory device configuration-byte writes must be constrained to addresses 0x2 through 0xf, as shown in table 8-7 . attempts to write outside this address space will result in undefined operation. configuration-byte writes only overwrite at2lp configuration byte registers, the original data source (i 2 c memory device) remains unchanged. 8.6.2 read_config_data this usb request allows data retrieval from the data source specified by the wvalue field. data is retrieved beginning at the address specified by the windex field. the wlength field denotes the length in bytes of data requested from the data source. legal values for wvalue are as follows: 0x0000 configuration bytes, addresses 0x0 ? 0xf only 0x0002 external i 2 c memory device illegal values for wvalue will result in undefined operation. attempted reads from an i 2 c memory device when none is connected will result in undefined operation. attempts to read configuration bytes with starting addresses greater than 0xf will also result in undefined operation. 9.0 absolute maximum ratings storage temperature .................................. ?65 c to +150 c ambient temperature with power supplied ..... 0 c to +70 c supply voltage to ground potential .............?0.5 v to +4.0 v dc input voltage to any input pin ............................... 5.25 v dc voltage applied to outputs in hi-z state......................................... ?0.5 v to v cc + 0.5 v power dissipation..................................................... 300 mw static discharge voltage.......................................... > 2000 v max output current per i/o port (d0-d7, d8-15, ata control)........................................ 10 ma 10.0 operating conditions t a (ambient temperature under bias) ............. 0c to +70c supply voltage ...........................................+3.15v to +3.45v ground voltage ................................................................. 0v f osc (oscillator or crystal frequency) .... 24 mhz 100 ppm, .................................................................. parallel resonant table 8-7. eeprom-related vendor-specific commands label bmrequesttype brequest wvalue windex wlength data load_config_data 0x40 0x01 0x0000 30x02 ? 0x0f data length configuration data read_config_data 0xc0 0x02 data source starting address data length configuration data
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 31 of 36 12.0 ac electrical characteristics 12.1 usb transceiver complies with the usb 2.0 specification. 12.2 ata timing the ata interface supports ata pio modes 0, 3, and 4, ultra dma modes 2, 3, and 4, and multiword dma mode 2 per the ata/atapi 6 specification. the at2lp will select the highest common transfer rate. 13.0 ordering information 11.0 dc characteristics parameter description conditions min. typ. max. unit v cc supply voltage 3.15 3.3 3.45 v v cc ramp supply ramp-up 0v to 3.3v 200 s v ih input high voltage 2 5.25 v v il input low voltage ?0.5 0.8 v i i input leakage current 0 < v ih < v cc 10 a v ih_x crystal input high voltage 2 5.25 v il_x crystal input low voltage -0.5 0.8 v oh output voltage high i out = 4 ma 2.4 v v ol output voltage low i out = ?4 ma 0.4 v i oh output current high 4ma i ol output current low 4ma c in input pin capacitance all but d+/d? 10 pf d+/d? 15 pf i susp suspend current connected: 300 380 a CY7C68300B/cy7c68320 disconnected: 100 150 a suspend current connected: 0.5 1.2 ma cy7c68301b/cy7c68321 disconnected: 0.3 1.0 ma i cc supply current usb high speed: 50 85 ma usb full speed: 35 65 ma i unconfig unconfigured current current before device is granted full current requested in bmaxpower 43 ma t reset reset time after valid power v cc > 3.0v 5.0 ms pin reset after power-up 200 s part number package type gpio pins CY7C68300B-56pvxc 56 ssop lead-free for self- and bus-powered designs ? cy7c68301b-56pvxc 56 ssop lead-free for battery-powered designs ? CY7C68300B-56lfxc 56 qfn lead-free for self- and bus-powered designs ? cy7c68301b-56lfxc 56 qfn lead-free for battery-powered designs ? cy7c68320-56lfxc 56 qfn lead-free for self- and bus-powered designs 3 [4] cy7c68321-56lfxc 56 qfn lead-free for battery-powered designs 3 [4] cy7c68320-100axc 100 tqfp lead-free for self- and bus-powered designs 6 cy7c68321-100axc 100 tqfp lead-free for battery-powered designs 6 cy4615b ez-usb at2lp reference design kit n/a note: 4. the general purpose inputs can be enabled on atapuen, pwr500#, and drvpwrvld via eeprom byte 8, bit 7 on cy7c68320/cy7c68321.
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 32 of 36 14.0 package diagrams 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-*a figure 14-1. 100-lead thin plastic quad flatpack (14 x 20 x 1.4 mm)
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 33 of 36 14.0 package diagrams (continued) 51-85062-*c figure 14-2. 56-lead shrunk small outline package 056 0.80[0.031] 7.70[0.303] 7.90[0.311] a c 1.00[0.039] max. n seating plane n 2 0.18[0.007] 0.50[0.020] 1 1 0.08[0.003] 0.50[0.020] 0.05[0.002] max. 2 (4x) c 0.24[0.009] 0.20[0.008] ref. 0.80[0.031] max. pin1 id 0-12 6.45[0.254] 8.10[0.319] 7.80[0.307] 6.55[0.258] 0.45[0.018] 0.20[0.008] r. 8.10[0.319] 7.90[0.311] 7.80[0.307] 7.70[0.303] dia. 0.28[0.011] 0.30[0.012] 6.55[0.258] 6.45[0.254] 0.60[0.024] top view bottom view side view e-pad (pad size vary by device type) 51-85144-*d figure 14-3. 56-lead qfn 8 x 8 mm lf56a dimensions are in millimeters
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 34 of 36 15.0 pcb layout recommendations the following recommendations should be followed to ensure reliable high-performance operation. at least a four-layer impedance controlled board is required to maintain signal quality. specify impedance targets (ask your board vendor what they can achieve). to control impedance, maintain uniform trace widths and trace spacing. to minimize reflected signals, minimize the number of stubs. connections between the usb connector shell and signal ground must be done near the usb connector. use bypass/flyback capacitors on vbus near the connector. dplus and dminus trace lengths should be kept to within 2 mm of each other in length, with preferred length of 20 ? 30 mm. maintain a solid ground plane under the dplus and dmi- nus traces. do not allow the plane to be split under these traces. for a more stable design, do not place vias on the dplus or dminus trace routing. isolate the dplus and dminus traces from all other signal traces by no less than 10 mm. source for recommendations: ez-usb fx2 pcb design recommendations, ht- tp:///www.cypress.com/cfuploads/sup- port/app_notes/fx2_pcb.pdf. high-speed usb platform design guidelines, ht- tp://www.usb.org/developers/data/hs_usb_pdg_r1_0.pdf. 16.0 quad flat package no leads (qfn) package design notes electrical contact of the part to the printed circuit board (pcb) is made by soldering the leads on the bottom surface of the package to the pcb. hence, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. a copper (cu) fill is to be designed into the pcb as a thermal pad under the package. heat is transferred from the at2lp through the device?s metal paddle on the bottom side of the package. heat from here is conducted to the pcb at the thermal pad. it is then conducted from the thermal pad to the pcb inner ground plane by a 5 x 5 array of vias. a via is a plated through-hole in the pcb with a finished diameter of 13 mil. the qfn?s metal die paddle must be soldered to the pcb?s thermal pad. solder mask is placed on the board top side over each via to resist solder flow into the via. the mask on the top side also minimizes outgassing during the solder reflow process. for further information on this package design please refer to the application note surface mount assembly of amkor?s microleadframe (mlf) technology . the application note provides detailed information on board mounting guidelines, soldering flow, rework process, etc. figure 16-1 displays a cross-sectional area underneath the package. the cross section is of only one via. the solder paste template needs to be designed to allow at least 50% solder coverage. the thickness of the solder paste template should be 5 mil. it is recommended that ?no clean,? type 3 solder paste is used for mounting the part. nitrogen purge is recom- mended during reflow. figure 16-2 is a plot of the solder mask pattern and figure 16- 3 displays an x-ray image of the assembly (darker areas indicate solder.) 0.017? dia solder mask cu fill cu fill pcb material pcb material 0.013? dia via hole for thermally connecting the qfn to the circuit board ground plane. this figure only shows the top three layers of the circuit board: top solder, pcb dielectric, and the ground plane figure 16-1. cross-section of the area under the qfn package figure 16-2. plot of the solder mask (white area)
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 35 of 36 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress 17.0 other design considerations certain design considerations must be followed to ensure proper operation of the CY7C68300B/cy7c68301b. the following items should be taken into account when designing a usb device with the CY7C68300B/cy7c68301b. 17.1 proper power-up sequence power must be applied to the CY7C68300B/cy7c68301b before, or at the same time as the ata/atapi device. if power is supplied to the drive first, the CY7C68300B/cy7c68301b will start up in an undefined state. designs that utilize separate power supplies for the CY7C68300B/cy7c68301b and the ata/atapi device are not recommended. 17.2 ide removable media devices the CY7C68300B/cy7c68301b does not fully support ide removable media devices. changes in media state are not reported to the operating system so users will be unable to eject/reinsert media properly. this may result in lost or corrupted data. 17.3 devices with small buffers the size of the ata/atapi device?s buffer can greatly affect the overall data transfer performance. care should be taken to ensure that devices have large enough buffers to handle the flow of data to/from the drive. the exact buffer size needed depends on a number of variables, but a good rule of thumb is: (aprox min buffer) = (data rate) * (seek time + rotation time + other) where other may include things like time to switch heads, power-up a laser, etc. devices with buffers that are too small to handle the extra data may perform considerably slower than expected. 18.0 disclaimers, trademarks, and copy- rights purchase of i 2 c components from cypress or one of its sub- licensed associated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system provided that the system conforms to the i 2 c standard specification as defined by philips. microsoft and windows are registered trademarks of microsoft corporation. apple and mac os are registered trademarks of apple computer, inc. ez-usb at2lp, ez-usb at2, ez-usb fx2 and ez-usb tx2 are trademarks, and ez-usb is a registered trademark of cypress semiconductor corporation. all product and company names mentioned in this document are the trade- marks of their respective holders. figure 16-3. x-ray image of the assembly
CY7C68300B/cy7c68301b cy7c68320/cy7c68321 document 38-08033 rev. *c page 36 of 36 document history page description title: CY7C68300B, cy7c68320 ez-usb at2lp? usb 2.0 to ata/atapi bridge document number: 38-08033 rev. ecn no. issue date orig. of change description of change ** 129739 12/04/03 gir new data sheet *a 215125 see ecn kku added hid descriptor, content security methods descriptor, alternate functions on 3 pins, and alternate eeprom addressing *b 274109 see ecn ari incorporated cy7c68320 information. updated graphics to reflect this change *c 318133 see ecn gir incorporated cy7c68301b and cy7c68321 information. updated graphics to reflect this change. revised data for final release and posting to website.

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